MemryX maps neural networks across distributed compute and memory, then executes them as data becomes available.
The model defines the flow. The compiler maps the neural network across the accelerator, and at runtime computation progresses as the data each mapped operation needs becomes available.
No central memory, no router, no instruction fetch. Producers write into the shared memory beside them, consumers start on the first quantum that lands, and the whole graph runs as one continuous pipeline.
Every trained model already describes how its data moves.
The graph names each operation and the tensors it consumes.
Producer and consumer relationships are fixed before anything runs.
None of this is MemryX-specific — it is the network you trained.
Mapped ahead of time and driven by data, the architecture pays off in four ways.
Performance
Data stays next to the compute that uses it and more of the chip stays busy, so more work gets done for less energy.
Accuracy
Feature maps stay in a floating-point format, so accuracy holds without a calibration dataset.
Model support
The compiler maps and adapts your network to the hardware, so a broad range of models runs efficiently.
Scalability
The same execution model extends from one chip to cascaded chips that act as one logical device, with no host orchestrating each stage.
Hardware, memory and compiler work together, so a model is mapped once and runs as a continuous, data-driven pipeline.
The compiler places the whole graph.
CompilerData sits beside the compute that uses it.
On-chip memoryNo instruction fetch, no scheduler.
Dataflow coresBF16 feature maps, quantized weights.
Hybrid precisionNear-memory and at-memory compute are part of this system — an important enabler of efficient dataflow execution, not the architecture’s defining idea.
Compile a network once and run it from a 3 W module to cascaded accelerators. The toolchain is a free download.
Cascade modules ship through our distribution partners. Pick the channel that suits your region and order volume.
